Almost done with the semester. Since finals are approaching, here’s a quick update:

  • I’ve kept punting the camera module debugging. I tried ordering another module to see if it was a hardware issue, but it seems to have gotten lost in the mail?
  • With regards to the GameTank verilog port, I’ve started porting over a 6502 CPU core into system verilog. The reasoning behind this is twofold: to get a better understanding of the 6502, and also to add a global enable to the module.
  • I finished reading the operating systems book. Once the semester is done, I should take another crack at the labs